Ultra Port Architecture
The Ultra Port Architecture (UPA) bus was developed by Sun Microsystems as a high-speed graphics card to CPU interconnect, beginning with the Ultra 1 workstation in 1995.
See also
External links
- UPA Bus Whitepaper
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Technical and de facto standards for wired computer buses
- System bus
- Front-side bus
- Back-side bus
- Daisy chain
- Control bus
- Address bus
- Bus contention
- Bus mastering
- Network on a chip
- Plug and play
- List of bus bandwidths
- SS-50 bus
- S-100 bus
- Multibus
- Unibus
- VAXBI
- MBus
- STD Bus
- SMBus
- Q-Bus
- Europe Card Bus
- ISA
- STEbus
- Zorro II
- Zorro III
- CAMAC
- FASTBUS
- LPC
- HP Precision Bus
- EISA
- VME
- VXI
- VXS
- NuBus
- TURBOchannel
- MCA
- SBus
- VLB
- HP GSC bus
- InfiniBand
- Ethernet
- UPA
- PCI
- PCI Extended (PCI-X)
- PXI
- PCI Express (PCIe)
- AGP
- Compute Express Link (CXL)
- Direct Media Interface (DMI)
- RapidIO
- Intel QuickPath Interconnect
- NVLink
- HyperTransport
- Intel Ultra Path Interconnect
- Coherent Accelerator Processor Interface (CAPI)
- SpaceWire
- ST-506
- ESDI
- IPI
- SMD
- Parallel ATA (PATA)
- Bus and Tag
- DSSI
- HIPPI
- Serial ATA (SATA)
- SCSI
- ESCON
- Fibre Channel
- SSA
- SATAe
- PCI Express (via AHCI or NVMe logical device interface)
- Multidrop bus
- CoreConnect
- AMBA (AXI)
- Wishbone
- SLIMbus
Interfaces are listed by their speed in the (roughly) ascending order, so the interface at the end of each section should be the fastest.
Category
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